Hi there 👋

These are my notes, interpretations, and ideas gathered from reading, learning, and building. I share them hoping they’re useful to others. Where ever I recall sources, I’ll link them. Credit goes to the many whose work and knowledge I’ve learned from; any mistakes or misunderstandings are mine alone. When you spot an error or have a correction, please share it; feedback helps us all learn better.

Optimizing a Lock-Free SPSC Queue

Yet another SPSC blog! The goal isn’t just to explain a final solution, such as the lock-free, index-cached implementation some of you might already know. Instead, I want to walk through the iterative process: testing different approaches, analyzing the results, and determining how to squeeze out performance. By walking through the analysis, I hope this process provides a template for tackling similar performance challenges in the future. The optimization discussions are focused on the x86 architecture. All measurements were taken on an AMD Ryzen 7 6800HS using gcc 13.3.0. This CPU has a single CCX (Core Complex), and the benchmarks use cores 0 and 2 - two distinct physical cores, rather than hyperthreaded siblings. ...

March 30, 2026 Â· 20 min